This invention relates to a method of manufacturing a semiconductor device having a non-volatile memory cell transistor with an insulated floating gate and a control gate and a MOS transistor with a single insulated gate on the same semiconductor substrate, and more particularly to a method of manufacturing a semiconductor device in which high (or high withstand) voltage MOS transistors can be integrated on the same semiconductor substrate without changing the characteristic of a non-volatile memory cell transistor.
Previously known LSI memories are non-volatile semiconductor memories such as a mask ROM, PROM (Programmable ROM), EPROM (Erasable and Programmable ROM), EEPROM (Electrical Erasable and Programmable ROM), etc.
Particularly, in the EPROM or EPROM, data storage is carried out in such a manner that charges are accumulated on the floating gate and a change in a threshold voltage due to the presence or absence of the charges is detected by the control gate. The EEPROM includes a flash EEPROM (that is also referred to a flash memory) in which data are erased for the whole memory chip or for each of some blocks into which an non-volatile semiconductor memory cell array are divided.
The non-volatile memory cells which constitute the flash EEPROM are roughly classified into a split gate type and stack gate type. The split gate type flash EEPROM is disclosed in WO92/18980 (G11C13/00). FIG. 12 shows a sectional structure of a split gate type non-volatile semiconductor memory cell 101 described in the publication WO92/18980.
For example, an N type source S and an N type drain D are formed on a P type single-crystal silicon (Si) substrate 102. A floating gate FG is formed through a first insulating film 103 on a channel CH formed between the source S and drain D. A control gate CG is formed through a second insulating gate 104 on the floating gate FG.
The control gate CG is partially arranged through the first insulating film on the channel CH so as to constitute a selecting gate 105. Storage of data is carried out in such a manner that hot electrons are injected into the floating gate FG encircled by the second insulating film (“tunneling insulating film”).
On the other hand, the data accumulated in the floating gate are erased in such a manner that a prescribed voltage is applied to the control gate CG so as to cause a tunneling current to flow from the floating gate FG through the second insulating gate 104.
Meanwhile, in recent years, a system in which the above flash EEPROM is mounted on the logic IC or microcomputer has been developed rapidly. In such a system LSI, e.g. microcomputer operating at 5 V, there is a case where an external signal of 10 V is applied to its I/O circuit. This required a high withstand voltage to be newly added.
The high voltage MOS transistor has a higher gate withstand voltage than a conventional type MOS transistor formed on the same chip.
Further, it has been investigated to incorporate a circuit which has another function and operates at a high supply voltage in the microcomputer with the flash EEPROM mounted. For example, in the system for a portable telephone, a control circuit for a lithium battery is mounted a one-chip microcomputer. In this control circuit, a high voltage of about 30 V is applied to the MOS transistor constituting the control circuit so that the high voltage MOS transistor with a further improved withstand voltage (gate withstand voltage, source-drain withstand voltage) must be integrated on the same chip.
The high voltage MOS transistor (withstand voltage of e.g. 30 V), in which a high voltage is applied to the gate electrode, must have a thicker gate insulating film than that of the conventional type MOS transistor (withstand voltage of e.g. 5 V) which constitutes the logic circuit of the microcomputer.
However, addition of a step of gate oxidation dedicated to the high voltage MOS transistor gives rise to a problem of increasing the amount of heat treatment in the manufacturing process to change the characteristic of a non-volatile memory cell, e.g. the threshold voltage or the current value of the memory cell.